1. Field of the Invention
This invention relates generally to the design of data processing systems and similar structures, and more particularly to an automated technique for the design of a logic structure in a manner similar to the technique used by a design engineer.
2. Description of the Related Art
The design of digital logic circuits may be considered as a map of nodes and arcs, wherein the nodes are functional in nature and the arcs are connective in nature. For example, the functionality of a node may be that of an adder element, the adder element providing output signal in response to input signals. The adder element may be technology independent which, in the present context, means that the adder element has no physical characteristics associated therewith and therefore does not define a digital device. The technology independent adder element is functionally correct and has attributes, such as a shape, for use in drawings, simulation behavior, equivalent gate count, etc. If a digital device, with a defined technology, were available that exactly matched the behavior and the interface characteristics of the adder element, then the digital device could be substituted for the technology independent adder in the design of the circuit. This technique is used in the automated design of digital logic circuits of the prior art where the transformation from technology independent to technology dependent design is accomplished by the substitution of previously designed elements defined by a predetermined technology.
Referring next to FIG. 1, the procedure for synthesizing a logic circuit design according to the prior art is shown. Model definition data structures from a library of component definitions are entered into the data structures associated with the synthesis data base in step 11. In step 12, the information related to the instances of the circuit design, including the connectivity information, is entered in the data base. The instances of the circuit design are generally in a behavioral or functional form when entered in the synthesis data base. The synthesis procedure relates the instances of the circuit design to the model instances in step 13. In step 14, a set of rules for the synthesis procedure is applied to each of the model instances and the model instances are altered and connected in such a way as to maximize certain parameters such as size, path delay, power, etc. In step 15, the resulting circuit design is placed in a format that can control the automated fabrication of the circuit.
It will be clear that the procedure for synthesizing a circuit described in relation to FIG. 1 is severely limited. If a circuit designer were synthesizing the same functionally described circuit, a functional component might suggest a plurality of model instances. Some of the suggested model instances would be more suitable than others. In addition, upon application of rules to the design process, the circuit designer would not exercise all possible rules, but would use only the applicable rules. A circuit designer would typically transform the functional components into the most elemental model instance implementations and then attempt, by an iterative process, for example, to converge on an optimum design. The optimum design goal is typically a combination of physical component size along with physical data transmission time through the entire circuit. In addition, the circuit designer would investigate the neighbors of the each model instance to determine if additional improvement in the circuit design can be achieved by combining coupled model instances. The circuit designer would also investigate signal paths whether in the direction of the signal flow or in the opposite direction from the signal flow.
A need, therefore, has been felt for a data base structure and an accompanying synthesis procedure that achieves additional flexibility and performance by utilizing techniques more closely mimicking the techniques of a circuit design engineer.